1. Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of etching contact holes whereby improved control of the Critical Dimensions of the opening of the contact hole is achieved.
2. Description of the Prior Art
With the continued decrease in semiconductor devices and the dimensions of the elements that are part of these devices, it is becoming increasingly more difficult to create openings in the various layers of the devices such that these openings do not interact around the upper perimeter of the openings. To avoid such interaction for very closely spaced openings, it is therefore not only important that merging of densely spaced openings is avoided but that in addition the openings are created having extremely vertical walls while being devoid of rounding of the walls of the openings where these walls approach the upper regions of the openings.
Increased semiconductor density has over the years resulted in the creation of multilevel devices wherein overlying metallic conductive layers are used to interconnect device elements. The adjacent and overlying patterns of interconnect metal are separated by layers of Inter Metal Dielectric (IMD), connections between adjacent and overlying layers of interconnect metal are established by creating contact holes or vias through the layers of IMD. By filling the holes or vias with a conductive material such as metal, overlying interconnect lines are connected together forming an interconnect network of increased functional capability.
With the extreme reduction in device features, the contact holes and vias must be created such that the openings of these holes and vias are as small as possible. With sub-micron device features, these openings have been reduced to having a diameter of 0.25 xcexcm of less. For such small openings, borderless contact holes are most frequently used in order to optimize the use of the available surface area of the semiconductor surface into which the hole is created. Openings that are created through overlying layers of semiconductor material are created in order to make electrical contact with a point of contact that is provided at the bottom of the opening. For instance, holes can be created through a layer of IMD to contact source and drain regions or the gate electrode of a Metal Oxide Semiconductor (MOS) device. Etch stop layers, typically comprising silicon nitride, are used to control the depth of the etch that is performed through the layer of IMD. The method of choice that is most frequently used to create openings uses photolithography whereby a pattern that is contained in a mask is transferred to a radiation sensitive medium, such as photoresist. The processing sequence can be summarized as follows: a semiconductor surface, most typically the surface of a monocrystalline silicon substrate, is provided, points of electrical contact have been provided in or on the surface of the substrate. A layer of etch stop material, such as silicon nitride, is deposited over the surface of the substrate, a layer of dielectric such as silicon oxide is deposited over the surface of the etch stop layer. A layer of photoresist is deposited over the layer of dielectric and exposed by a light source that exposes the surface of the layer of photoresist through a mask. The regions of the layer of photoresist that are exposed by the light source change in their molecular composition such that this exposed photoresist can be readily removed from the surface of the layer of dielectric. After this exposed photoresist has been removed, the layer of dielectric can now be etched, stopped by and thereby partially exposing the surface of the etch stop layer in a pattern that aligns with the points of electrical contact that have been provided in the surface of the substrate. By removing the etch stop layer from the bottom of the openings that have been created through the layer of dielectric, the points of electrical contact in the surface of the substrate are exposed. Filling the openings in the layer of dielectric with a electrically conductive material such as metal and polishing this layer of electrically conductive material down to the surface of the layer of dielectric leaves in place electrically conductive plugs through the layer of dielectric that contact the points of electrical contact in the surface of the substrate. The layer of conductive material that has been deposited to fill the openings that have been created in the layer of dielectric can further be patterned and etched, interconnecting the conductive plugs with an overlying network of interconnect lines.
The technology of photolithography has also been adopted in order to create openings of smaller dimension and in a denser pattern of openings. Smaller wavelengths for the exposing light source, such as the use of Extreme Ultra Violet (EUV) light with a wavelength of about 50 to 700 Angstrom, has been applied for this purpose. This approach however has the limitation that shorter wavelengths of the exposing light source limits the depth to which the light can penetrate the exposed surface, such as the surface of a layer of photoresist. This in turn limits the thickness of the layer of photoresist that can be used, which limits the etch protection that the layer of photoresist provides.
It has previously been stated that the method of photoresist uses a mask to transpose a pattern that is contained in the mask to a surface, such as the surface of a layer of photoresist. This brings with it the requirement that the image that is created by the mask on the exposed surface must be positioned (aligned) with extreme accuracy so that the exposed surface of the layer of photoresist aligns most closely with the points of electrical contact to which a conductive plug must be established. For practical applications, some consideration must therefore be given to misalignment of the exposure mask with the target points of electrical contact. For this reason, regions that must not be etched and where no opening for a contact plug is to be created are at times surrounded with an etch resistant material so that incorrect alignment still allows for the creation of holes of proper alignment.
The methods of etching that have most recently been used for the creation of the openings for contact plug are methods of dry etching such as plasma etching and Reactive Ion Etching (RIE). These methods of dry etching can be highly selective in the materials that are being etched but can also provide an etch that is highly anisotropic, resulting in holes that have nearly vertical sidewalls. However, dry etches are expensive due to the high cost of Reactive Ion Etching (RIE) systems and are limited in application because they require a hard mask.
A hard mask is used in the creation of semiconductor features because it is opaque to the photochemical light that is used in photolithography. Light will therefore not be reflected from the hard mask layer which, in typical applications that use for instance polysilicon or polycide as layers of conductive material, causes a problem of light diffusion and therefore poor definition of the exposed pattern with a resulting poor definition of the hole that is created.
The basic procedure that is used for a sequence of dry etching uses a processing chamber into which the semiconductor surface, on which the various layers that need to be etched have been deposited, is positioned on a first electrode. A second electrode of the processing chamber is positioned opposite the first electrode. A gaseous medium containing the etchant gasses is passed through the processing chamber while at the same time a rf voltage is applied between the first and the second electrodes in order to activate (ionize) the etchant gasses, forming a plasma that etches the layers on the surface of the semiconductor surface. The etchant gasses are selected for optimum results and are dependent on the material of the layer that needs to be etched. By proper selection of these gasses, selective and anisotropic etching of the successive layers can be accomplished.
U.S. Pat No. 6,127,070 (Yang et al.) shows a via etch process using a nitride hard mask.
U.S. Pat. No. 5,611,888 (Bosch et al.), U.S. Pat. No. 6,077,790 (Li et al.) and U.S. Pat No. 6,147,007 (Yang et al.) show other via etch process using hard masks.
A principle objective of the invention is to provide a method for the creation of openings whereby improved control of the Critical Dimensions (CD) of the opening is achieved.
Another objective of the invention is to provide a method for the creation of ultra-small openings whereby these openings can be created in a dense pattern without causing problems of merging of adjacent openings.
Yet another objective of the invention is to provide a method for the creation of ultra-small openings whereby rounding of the upper regions of the sidewalls of the openings is reduced, thereby reducing the occurrence of key holes in the formation of metal plugs inside these openings.
In accordance with the objectives of the invention a new processing sequence is provided for the creation of openings in layers of dielectric. The invention provides the steps of, over a semiconductor surface, depositing an etch stop layer over which a layer of dielectric is deposited over which a hard mask layer is deposited. A layer of photoresist is deposited and patterned on the surface of the hard mask layer, an opening is etched in the hard mask layer, the photoresist is removed after which the main opening is etched through the layer of dielectric and the etch stop layer. The surface is wet cleaned, after which, significantly as a processing step of the invention, a thin layer of silicon oxide is CVD deposited over the inside surfaces of the created opening. This thin layer of CVD oxide provides control of the critical dimensions of the upper region of the opening (that has been etched through the layer of dielectric and the etch stop layer) and further provides profile control of the opening itself. After this, the processing continues with a pre-barrier metal argon sputter. This pre-barrier metal argon sputter optimizes the profile of the cross section of the opening by partially removing the deposited thin layer of oxide from the sidewalls of the opening and by removing the thin layer of oxide from the bottom of the opening. Then the process continues with the deposition of the barrier metal, the filling of the opening with a conducting material to create the metal plug and the polishing of the surface of the deposited conducting material.